App note: Clearing Xilinx FPGA configuration to allow boundary scan testing

Another application note from XJTAG on preparing Xilinx FPGA for proper boundary scan testing. Link here

When Xilinx FPGAs are configured it can restrict the boundary scan access to some signals on the device. One work-around for this problem is to configure the FPGA with a ‘blank’ image that closely matches its unconfigured state, allowing boundary scan testing to occur without any problems.

A second issue that can affect boundary scan testing with FPGAs is that they contain pull resistors. Depending on the design, these may be enabled when the FPGA is unconfigured as well as when it is configured. If these internal resistors are enabled on nets that contain pull resistors mounted on the board, two potential problems can occur:

1. If the internal resistor and external resistor pull in opposite directions, the boundary scan tests may not be able to test the external pull resistor if it is weaker than the internal pull resistor.
2. If the internal and external resistors pull in the same direction, a fault with the external resistor may not be detected because the internal resistor may mask the fault.

By setting the correct configuration options it is possible to disable these internal pull resistors when generating a ‘blank’ FPGA image.

from Dangerous Prototypes http://ift.tt/2up4lBM

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