BUS PIRATE: pipelined and non-pipelined commands

Bus Pirate prototype Ultra v1b uses an FPGA to process commands sent through a FIFO buffer to a state machine. Pipelined commands can be loaded into the FIFO and executed by the state machine with per-clock repeatability. Non-pipelined commands halt the state machine while the MCU takes over to perform the command, the delay is unpredictable and depends on many factors such as USB operations the MCU may be servicing.

These commands are currently pipelined and handled in the FPGA by the state machine:

  • Delays (ms, us)
  • Bus reads
  • Bus writes
  • Pin read/write/direction

These commands can be pipelined, but are currently handled in registers:

  • PWM
  • Frequency measurement

These commands will be pipelined in v1c and later:

  • ADC reads (on any pin, Vout)

These commands could be pipelined with some hardware updates:

  • Pull-up resistors toggle
  • Power supply enable
  • Power supply margining (by adding an external DAC)

These commands cannot be pipelined because they happen outside the FPGA:

  • Mode change (reloads the FPGA)
  • Reset
  • Jump to bootloader
  • Self-test (involves tests on the MCU and FPGA)

There are also mode macros to consider, which probably need to be a combination of pipelined commands and non-pipelined commands. This week we’ll choose an external DAC and add it to the board.

from Dangerous Prototypes https://ift.tt/2MRG6XB